Study on Stability Analysis and Defect Effect of Low Temperature Polycrystalline Silicon Thin-Film Transistors

• Main Authors: Yang, Wei-Jhe, 楊維哲
• Other Authors: Liu, Po-Tsun
• Format: Others
• Language: en_US
• Published: 2009
• Online Access: http://ndltd.ncl.edu.tw/handle/91572118371567297641

碩士 === 國立交通大學 === 顯示科技研究所 === 97 === As the large demand of liquid crystal display in recent years, many research organization and corporation have invest in new technique. So the function of display changes with each passing day, from simple display and projection to the popular touch panel at the present day. The ideal dream of display is one combined with system package and panel on a glass which is so called SOP (system on panel). Now the amorphous silicon thin-film transistor is the main flow on business situation. Polycrystalline thin-film transistor has low market share for high cost. But amorphous thin-film transistor has problem of only N-type and the slow mobility, it is unsuitable for circuit application. For Polycrystalline thin-film transistor, it has the P-type and N-type for CMOS circuit composition. Moreover, the carrier mobility is much fast than a-Si. Now, some peripheral circuit has fabrication on panel with poly-Si. In this thesis, the motivation is because poly-Si TFT for circuit application whether digital or analog circuits will face to gate bias stress induced degraded problem on circuit working. And the panel’s poor thermal conductance will caused high temperature. Therefore, the degrade influence combines with gate bias and temperature. The life time of device on operation has to be concerned. We discuss two type of TFT：N and P at positive and negative gate bias and source drain ground condition. And then at different temperature and time we confer the different degrade phenomenon. This is like NBTI(Negative Bias temperature instability) and PBTI(Positive Bias temperature instability) in conventional MOSFET, just the difference of higher temperature and stressed voltage. We discuss the influence of NBTI on PTFT. Using a simple mathematical formula describes the correlation of threshold voltage, temperature, voltage and time. And explanting it by acknowledged NBTI on p-MOSFET theory. However, the polycrystalline has not only interface of silicon dioxide and polycrystalline but also grain boundary, so it is necessary to concern grain boundary for degradation. Afterward, phenomenon of PBTI on NTFT, PBTI on PTFF and NBTI on NTFT is explained and compared one by one. Besides, we further analyze the type and quantity of defect. In the measure process, it involves commonly basic electric analysis for IV curve, CV analysis and extracts the traps amount of grain boundary and interface from IDVG curve. Additionally, we introduce the gated PIN diode which has electron source and hole source, using the PIN structure, we can use charge pumping measurement. This technique can further understand the type (donor or acceptor) and qualitative and quantitative analysis. Finally, thoroughly comparing and analyzing the degrade mechanism of the four conditions and distinguishing each degrade mechanism.