Effect of PECVD Passivation Layer Stress/Deformation on The Threshold Voltage Shift of MOS
碩士 === 國立交通大學 === 工學院碩士在職專班半導體材料與製程設備組 === 97 === For semiconductor fabrication process of 0.5μm critical dimension, in general, for protecting the device circuits issue, the foundry uses the Plasma Enhanced Chemical Vapor Deposition (PECVD) to deposit the passivation layer with multi structure. The...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2009
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/73967480355731272697 |