Low Power High Density 6-bit 1GS/s A/D D/A converters

• Main Author: 李家昕
• Other Authors: 洪浩喬
• Format: Others
• Language: zh-TW
• Published: 2009
• Online Access: http://ndltd.ncl.edu.tw/handle/71108447694411042203

碩士 === 國立交通大學 === 電機學院碩士在職專班電機與控制組 === 97 === This thesis presents a pair of low power,high density 6-bit 1GS/s analog-to-digital converter (ADC) and digital-to-analog converter (DAC). Both data converters are realized in tsmc 0.13um CMOS Mixed-Signal/RF 1P8M process. The ADC is a flash type ADC with averaging and interpolating techniques. Averaging and interpolating techniques can reduce the number of amplifiers used to reduce the power and enhance the linearity. We use a direct encoder to reduce the logic power in the ADC design. The DAC is realized with the current-steering architecture. For the DAC design, we use a hybrid decoder to reduce layout area and cascode output current sources to achieve a higher output impedance. The proposed data converter pair can provide 6-bit resolution and is for the implementation of the baseband data transceiver in ultra-wideband communication systems. Under a 1.2V supply and 1GS/s sampling rate, the measured results in the ADC cascading DAC mode show that the data converter pair can archive an SFDR of 37dBc. The ADC consumes 46.37mW and DAC consumes 30.57mW in this testing mode, respectively.