| Summary: | 碩士 === 國立交通大學 === 電信工程系所 === 97 === An efficient legalization approach is necessary for the integrated circuit design which consists of millions of movable standard cells and fixed macros. To maintain the global placement result, the disturbance of cells must be minimized. In this work, a fast legalization placer, FastLegalize, is developed to legalize standard cells with minimal movement.
First, a chip is divided into several bins with equal size to limit the movable scope of cells. Then, starting with the most crowed unlegalized bin, a merging procedure for bins is used to integrate bins into a cross-shaped bin-merged structure or a square-shaped bin-merged structure until the cell density in that bin-merged structure is less than a defined threshold. After that, an efficient legalization method which simultaneously preserves the ordering in each row and minimizes the sum of absolute movement distances is developed to legalize cells in that bin-merged structure. To improve the legalization quality, the proposed legalization method refreshes the positions of legalized cells during legalization. Finally, the above legalizing procedure is repeated until all cells are non-overlapped.
Compared with the state-of-the-art method, Abacus, FastLegalize can reduce the total movement of cells to be 48% in average, and save the largest movement of cells to be 140% in average. Moreover, FastLegalize can obtain average 1.11X runtime speed up.
|
|---|
