| Summary: | 碩士 === 國立交通大學 === 電信工程系所 === 97 === Low cost, high performance clock generators are required in high speed I/O interface and wireless communication receivers. The conventional clock generation is based on Phase-Locked Loop (PLL). The Oscillator in a PLL by using LC-tank, which achieves high phase noise performance is needed in high-quality wireless communication systems, but it comes with the cost of area and power consumption and the frequency multiplication factor cannot be changed once the LC-tank value is chosen. The ring oscillator for integrated PLLs has the advantages of less complexity and easiness to integrate, and thus becomes one of the most popular oscillators. Unfortunately, the phase noise of ring oscillators is inferior, impeding its use in high-quality communication systems..
Clock generation by Delay-Locked Loop (DLL) is adopted to achieve lower clock jitter than PLL because of no jitter accumulation. Furthermore, it occupies smaller area due to a simpler loop filter. Recently, DLL-based clock generators and a local oscillator have been proposed to overcome the difficulty of frequency multiplication which utilize the several inherent advantages of DLLs over PLLs. We design and analyze a DLL-based clock generator that achieves a 0.5X-based frequency multiplication factor up to 4X and provides the output clock frequency operating range from 150MHz to 1200MHz. Furthermore, the clock generator achieves fast clock frequency scaling in one clock cycle under the situation: the multiplication factors of 0.5X, 1X, 2X, 4X or 1.5X, 3X are chosen. The chip has been fabricated with TSMC 0.18μm 1P6M CMOS technology.
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