Design and Analysis of A DLL-based Clock Generator for Dynamic Frequency Scaling
碩士 === 國立交通大學 === 電信工程系所 === 97 === Low cost, high performance clock generators are required in high speed I/O interface and wireless communication receivers. The conventional clock generation is based on Phase-Locked Loop (PLL). The Oscillator in a PLL by using LC-tank, which achieves high phase no...
| Main Authors: | , |
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| Format: | Others |
| Language: | en_US |
| Published: |
2008
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| Online Access: | http://ndltd.ncl.edu.tw/handle/81809868075407980563 |