Study on the Low-Temperature Polycrystalline Silicon Thin-Film-Transistors with Single Grain Boundary in the Channel for the SONOS Memory Application

• Main Author: 鄧茜云
• Other Authors: 鄭晃忠
• Format: Others
• Language: en_US
• Published: 2009
• Online Access: http://ndltd.ncl.edu.tw/handle/37019325111713513034

碩士 === 國立交通大學 === 電子工程系所 === 97 === Low-temperature polycrystalline silicon (LTPS) thin film transistors (TFTs) were the important devices in flat-panel displays, system on a panel (SOP), and three dimensional integrated circuits (3D-ICs) applications due to their high field-effect mobility. However, there was high performance of operating element as well as memory in the SOP, so the TFT-SONOS memory is worthy to investigate. Although amorphous silicon thin film can convert to polycrystalline silicon thin film by excimer laser crystallization, there were still some drawbacks such as narrow process window, random grain boundaries, etc. In this thesis, single grain boundary (SGB) double gate (DG) thin-film transistor (TFT) SONOS memory was fabricated by excimer laser annealing. In addition, the double-gated configuration was also studied. The electrical characteristics, programming and erasing characteristics, and reliability of SGB-DG-TFT-SONOS memory were studied and discussed in detail. In the first part, SGB-DG-TFT memory fabricated by excimer laser annealing was investigated. The mechanisms of elevated channel thin films were studied. In this method, a thick amorphous silicon region was formed in the both sides of elevated channel on the bottom gate which served as the seeds for the lateral grain growth during excimer laser irradiation. As the laser energy density was controlled to completely melt the thin region in the channel and partially melt the thick region near the corner, the lateral grain growth starting from the sides of elevated channel could progress along the direction toward the center of channel region. As the excimer laser energy was 620mJ/cm2 and the channel length was 1μm, 1.2μm, and1.5μm, there was only one longitudinal grain boundary in the center of the channel. Nevertheless, it cannot form a longitudinal grain boundary in the center of the channel with the channel length was 2μm and 3μm owing to the temperature dissipation. The electric characteristic of top gate structure, such as field-effect mobility is about 230cm2/V-s and the subthreshold swing is 0.116V/decade. To improve the gate controlling ability, we employ the double gate structure. The electric characteristic of top gate structure, such as field-effect mobility is about 488cm2/V-s and the subthreshold swing is 0.083V/decade. In the second part, to investigate and discuss the crystallinity of the device channel with excimer laser crystallized, we employed FN tunneling for programming and erasing operations in our device. The process window of SGB-DG-TFT-SONOS memory with excimer laser energy about 620mJ/cm2 and the programming voltage was 15V as the programming time of 10ms was 2V. Besides, we observed the better crystallinity of the device with excimer laser energy about 620mJ/cm2 compare with the device with excimer laser energy about 640mJ/cm2 and 600mJ/cm2. And the programming/ erasing speed of SGB-DG-TFT-SONOS memory with excimer laser energy about 620mJ/cm2 and the channel length was 1.5μm was faster. It should be noted, however, that the double-gated structure with ELC does not seem to improve the endurance characteristics and reliability characteristics of the device. The poor endurance and retention are ascribed to the poor quality of TEOS used for the tunneling oxide as well as the protrusion in the middle of the channel. The traps are easily generated because of poor quality of TEOS. Besides, high electric field due to the protrusion in the middle of the channel could damage the tunneling oxide. The benefits of the two parts I talked about above combined, SGB-DG-TFT-SONOS memories, will be the potential candidates of SOP in the future, therefore achieve their goal.