| Summary: | 碩士 === 國立交通大學 === 電子工程系所 === 97 === Embedded memory plays a significant role in high performance and low power VLSI technology. Stability and area of traditional 6T SRAM is difficult to scale down in future process due to the serious PVT variation and other effect, such as reliability issue: NBTI and PBTI. In this thesis, detailed analysis of timing control degradation caused by NBTI and PBTI on SRAM is presented. Furthermore, NBTI/PBTI tolerant design for nanoscale CMOS SRAM is also presented, which reduces 32%-48% degradation. Another method to address drawbacks of 6T SRAM cell is to design another new bit-cell, presented in this thesis. This new bit-cell eliminates read disturb and half-select disturb of 6T bit-cell and has 1.75X read SNM improvement when compared to the conventional 6T SRAM cell. An interface circuit design lets the unique structure of new 8T bit-cell combine the peripheral circuit of 6T SRAM without declining performance.
Another important SRAM design is multi-port SRAM-based register file. Similarly, multi-port bit-cell in nano-scale process or ultra low voltage works fail. As a result, a micro-watt multi-port register file with wide operating voltage range for micro-power applications is presented. Multibank architecture for simultaneous access with collision detecting technique is proposed. The architecture can be applied to VLIW DSP, and has been analyzed under wide operating voltage range between 1V to 0.25V with varies process corner. Negative voltage write scheme ensures successful write in deep sub-threshold region. Also, an improved read buffer footer and controllable pre-charge in read scheme are designed. A 4W/4R 16KB register file is implemented in UMC 90nm CMOS technology. The simulation results show that the maximum active power of multi-port register file can achieve near 22.3-22.9uW at 485 KHz under 0.25V.
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