| Summary: | 博士 === 國立交通大學 === 電子工程系所 === 97 === In this thesis, the design methodologies and implementations of millimeter-wave CMOS circuit for 60-GHz low-power communication system are presented. There are three parts: (1) the analysis, modeling, and design of the subharmonic injection-locked frequency tripler (ILFT); (2) the analysis and design of 60-GHz phase-locked loop (PLL) integrated with injection-locked frequency multiplier (ILFM); and (3) the design of 60-GHz direct-conversion receiver integrated with ILFT.
At first, K-band and V-band CMOS differential subharmonic ILFTs are proposed, analyzed, and designed. Based on the proposed ILFT structure, models for the locking range and the output phase noise are developed. A K-band ILFT is designed and fabricated using 0.18-μm CMOS technology. The measured locking range is 1092 MHz with a dc power consumption of 0.45 mW and an input power of 4 dBm. The harmonic rejection-ratios are 22.65, 30.58, 29.29, 40.35 dBc for the first, second, fourth, and fifth harmonics, respectively. The total locking range of the K-band ILFT can achieve 3915 MHz when the varactors are used and the dc power consumption is increased to 2.95 mW. A V-band ILFT is also designed and fabricated using 0.13-μm CMOS technology. The measured locking range is 1422 MHz with 1.86-mW dc power consumption and 6-dBm input power. It can be seen that the locking range of the proposed ILFT is similar to the tuning range of a conventional varactor-tuned bulk-CMOS voltage-controlled oscillator (VCO).
Secondly, a novel CMOS PLL integrated with ILFM that generates the 60-GHz output signal is proposed. The proposed 60-GHz PLL is composed of VCO, ILFM, 1/32 frequency divider, phase/frequency detector, charge pump, and loop filter. Because the proposed ILFM can generate the fifth-order harmonic frequency of VCO output, the operational frequency of the VCO can be reduced to only one-fifth of the desired frequency. The PLL is designed and fabricated in 0.18-μm CMOS technology. The output frequency range of the proposed PLL is from 53.04 GHz to 58.0 GHz with output power of –37.85 dBm. The measured phase noises at 1 MHz and 10 MHz offset from the carrier are –85.2 and –90.9 dBc/Hz, respectively. The reference spur level of –40.16 dBc is measured. The dc power dissipation of the fabricated PLL is 35.7 mW under a 1.8-V supply. The chip area including pads is 0.96 mm × 0.84 mm.
Finally, a 60-GHz direct-conversion receiver integrated with ILFT is proposed. The proposed direct-conversion receiver front-end is composed of a low-noise amplifier (LNA), I/Q quadrature down-conversion mixers, a 20-GHz QVCO, two ILFTs, two IF amplifiers, and two output buffers. In the proposed receiver, the local oscillator (LO) signals are generated by QVCO operated at only one-third of carrier frequency cascade with the two ILFTs. Due to the frequency shift of QVCO, the maximum RF frequency is only 55.03 GHz. The measured results show a receiver gain of 18.2 dB, a noise figure of 16.96 dB with RF frequency of 55.03 GHz and IF frequency of 100 MHz, channel bandwidth of 2 GHz with LO frequency of 55.02 GHz, an input-referred 1-dB compression point (P1dB) of –17.0 dBm, and input third-order inter-modulation intercept point (IIP3) of –7.6 dBm. The proposed receiver is implemented using 0.13-μm CMOS technology and draws 25.84 mA from a 1.2-V supply. The total chip area, including testing pads, is only 1.21 mm × 1.03 mm.
It is believed that the proposed ILFT can be used in low-power high-performance transceiver design in the millimeter-wave band. Further research for low-power single chip transceiver and frequency synthesizer can be integrated in the future.
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