| Summary: | 碩士 === 國立交通大學 === 電子工程系所 === 97 === As the technology scales down to nanometer, the yield degradation caused by inter-die variations is getting worse. Using adaptive body bias is an effective method to eliminate the yield degradation, however we need to know a die having high threshold voltage or low threshold voltage (also called process corner) in order to use this technique. Unfortunately, it is hard to detect the process corner when PMOS and NMOS variations are uncorrelated. In this thesis, we propose some improved circuits of delay monitor and leakage monitor for both PMOS and NMOS having inter-die variations, and are uncorrelated. The experimental results show that our circuits can clearly distinguish each process corner of PMOS and NMOS, thus improve the yield obviously by adopting correct body bias.
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