Multi-Gbps Equalizer Technology for Serial Link System

• Main Authors: Yu-Sam Huang, 黃喻暄
• Other Authors: Shyh-Jye Jou
• Format: Others
• Language: en_US
• Published: 2008
• Online Access: http://ndltd.ncl.edu.tw/handle/54739594271502580283

碩士 === 國立交通大學 === 電子工程系所 === 97 === In the multi-media era, many high-speed serial link trarnsmission technologies are developed and are widely used for high performance modern electronic product. In order to maintain the data quality that will be attenuated by communication channel, the equalizer becomes an important component in the high-speed serial link system. Based on the type of data processing, the equalizer can be categoried into continuous-time equalizer and discrete-time equalizer. In this thesis, we first propose a continuous-time qualizer that operates at 6 Gbps. We take a level-shifter stage in the front of our proposed equalizer for minimizing the DC voltage level variation in the equalizer input and for providing the low-frequency gain in the proposed circuit. In the equalization block, we use two serial cascade stages to minimize the gain suppression at low frequency while to boost the gain in high frequency. The proposed equalizer can compensate 13.87 dB channel loss at clock frequency of 3 GHz. The test chip is fabricated in UMC 90 nm CMOS regular-Vt process. The post-layout simulation results show that the data eye in the output of equazlier stage is about ±250 mV, and the data eye in the output of buffer stage can reach ±300 mV that meets our specification. Total area of our proposed equalizer including pads is 0.49 × 0.49 mm2 and power consumption is 78.83 mW under 1.0 V supply voltage. Secondly, we propose a hopping coefficients update and ping-pong coefficients update schemes for a discrete-time half-rate DFE (Decision-feedback equalizer) architecture [8]. The architecture uses five taps to cancel the ISI (intersymbol-interference) effects and uses the speculation method to relax the timing constrain. The algorithm used for coefficients update is the sign-sign LMS (least-mean-square) algorithm. For the hopping update scheme, the operation frequency of coefficients update block can be reduced and the power can be saved. For ping-pong update scheme, we calculate the sign of error under different conditions in these two data paths. The ping-pong update scheme saves one comparator for calculating the sign of error in each data path. For these two update schemes, we run different conditions and summary the convergent performance. We get the guideline of choosing parameters in the proposed equalizer under some system specifications especially the speed of convergence.