Design of Configurable I/O Cell Library in 90-nm CMOS Process

• Main Authors: Shih-Fan Chen, 陳世範
• Other Authors: Ming-Dou Ker
• Format: Others
• Language: en_US
• Published: 2008
• Online Access: http://ndltd.ncl.edu.tw/handle/76788094784891110431

碩士 === 國立交通大學 === 電子工程系所 === 97 === The cell library plays an important role in integrated circuits (ICs), because it includes all of fundamental cells to construct the ICs. In the cell library, the input/output (I/O) cells provide the link between the ICs and outward. Thus, the I/O cells are used to provide the driving currents, to receive the input signals, and to protect the ICs against electrostatic discharge (ESD) damages. As the feature size of MOS transistors shrinks with the advance of complementary metal-oxide-semiconductor (CMOS) technology, the circuit functions become more complex and the operating frequency becomes higher. However, thinner gate-oxide decreases the ESD robustness of MOS transistors. Hence, there are more challenges and limits for the I/O cell library design in nanoscale CMOS technology. In this thesis, an I/O cell library is designed in 90-nm CMOS technology. The I/O cell library includes the configurable I/O cells, analog I/O cells, power cells, and power break cell. In the configurable I/O cell, the output stage is used to provide driving current. Besides, it can pull the I/O pad up to logic high or pull the I/O pad down to logic low under the tri-state. In input stage, a schmitt-trigger is realized and can be turned on to increase the noise margin of input signal. All of the aforementioned functions have been integrated in a single configurable I/O cell proposed in this thesis. Moreover, the ground bounce issue becomes more critical as the instantaneous driving current becomes larger. In the proposed I/O cell library, the slew-rate-control unit is realized in another configurable I/O cell to mitigate the ground bounce issue. In addition, several effective ESD protection circuits are designed in this I/O cell library to provide whole-chip ESD protection. The proposed I/O cell library has been fabricated in 90-nm CMOS process. Experimental results have successfully verified all of the functions provided in the I/O cell library, including receiving input signals, transmitting output signals, slew-rate control, and whole-chip ESD protection.