| Summary: | 碩士 === 國立交通大學 === 電子工程系所 === 97 === As COMS devices are scaled aggressively into nanometer regime, the conventional SiO2 or SiON gate dielectrics are approaching their physical and electrical limits. The major issue is the intolerably huge leakage current caused by the direct tunneling of carriers through the ultrathin oxide. High permittivity materials as gate dielectrics have been proposed to offer thicker dielectric physical thickness with the desired equivalent oxide thickness in electrical properties and Hf-base high-k gate dielectrics have been recognized as the most promising candidates. However, the Hf-based high-k gate dielectrics are known to suffer from the reliability concern of threshold voltage instability due to the charge trapping and de-trapping in the pre-existing bulk traps in Hf-based high-k gate dielectrics. On the other hand, in order to retard the downscaling of Si based CMOS device, mobility enhancement is one of the most useful methods. Mobility enhancement techniques represent an effective and essential way to reduce Vdd and resulting power consumption without losing circuit performance.
First, one of the most popular mobility enhancement technologies is using high tensile-stress contact etch stop layer (CESL), which can obviously improve electron mobility and ION for nMOSFETs. The basic electrical properties and the charge trapping condition of strain effect are investigated in nMOSFETs. Next, the physical mechanisms of charge trapping and de-trapping can be investigated by fitting the data of the threshold voltage shifts versus stress/recovery time in nMOSFETs and pMOSFETs. Final, the basic electrical properties and the negative bias temperature instability of fluorine effect are investigated in pMOSFETs. Moreover, the fast charge trapping is investigated by pulsed I-V measurement.
|
|---|
