TLB with Low Miss Rate in Context Switching and Study of Implementation of Asynchronous Circuit

• Main Authors: Cheng, Wei-Min, 鄭緯民
• Other Authors: Chen, Chang-Jiu
• Format: Others
• Language: en_US
• Published: 2009
• Online Access: http://ndltd.ncl.edu.tw/handle/90449171456795827037

博士 === 國立交通大學 === 資訊科學與工程研究所 === 97 === Embedded processors are widely used in many embedded systems and handheld devices. Hence, low power, reliability, and robustness have been becoming the critical issues for these processors. Asynchronous circuits may be one of the best solutions to overcome these problems. Thus it may be more suitable to implement these processors with asynchronous circuits. It is widely known that these embedded processors are used to execute varieties of tasks. Recently, many new embedded systems and handheld devices begin to execute very complex operating systems, such as embedded Linux or Windows�� mobile. In order to support virtual memory mechanism of modern operating systems, address translation from virtual address to physical address should be supported. However, it is widely considered as the critical issue of memory system performance. In order to improve the address translation performance, the Translation Lookaside Buffer (TLB) is implemented inside almost all contemporary processors. In this work, we propose an alternative TLB architecture with low context switch miss rate for asynchronous embedded processors. We adopted a heuristic TLB banking designs to replace per-entry ASID to identify each address space. In addition, simple prefetching mechanism is used to reduce some possible compulsory misses. Because the architecture is designed for asynchronous embedded processors, all operations are very simple. Finally, we implemented the TLB controller for the proposed TLB architecture with Balsa HDL. Because we skillfully arrange the communication channels, we can verify the implementation easier with assumed random pattern. Though it’s possible to verify our implementation with such simple way, it’s impossible and unreasonable to verify the whole asynchronous embedded processor that we are currently working for. We also suggested a hardware/software co-design and cross-verification flow for our future work. Finally, the gate-level netlist was generated with Balsa tools, and the equivalent gate count of the implementation was estimated. The result shows that the cost of the implementation modeled with Balsa HDL is not cheap. The total equivalent gate count is 688,560. However, we also describe why designing asynchronous circuits with such high-level asynchronous HDL. It’s needed for future larger design!