Early Load：Hiding Load-to-Use Latency in Deep Pipeline Processors
碩士 === 國立交通大學 === 資訊科學與工程研究所 === 97 === In order to achieve high instruction throughput, high performance processors tend to use more and deeper pipelines. As pipeline gets deeper and wider, the instruction execution latency becomes longer. The longer instruction execution latency induces more pipel...
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| Format: | Others |
| Language: | en_US |
| Published: |
2008
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| Online Access: | http://ndltd.ncl.edu.tw/handle/87648186708460464578 |