| Summary: | 碩士 === 國立交通大學 === 電機學院IC設計產業專班 === 97 === ABSTRACT
H.264/AVC is a new generation video coding standard and is approved by ITU-T as Recommendation H.264 and by ISO/IEC as MPEG-4 Part 10 Advanced Video Coding. H.264/AVC is to achieve higher compression efficiency and provide the better video quality. Because the H.264 is an adoption block the mode does image processing. However, the most annoying artifact known as the blocking artifact also comes into existence. In order to solve this problem, the de-blocking filter is an important component of H.264/AVC to reduce the block artifacts. In the complexity simulation of H.264/AVC decoder part, the de-blocking filter is the most complexity part, probably has taken 36% execution time. Because of in the de-blocking filter data processing process has the repetition access appearance. In order to improve memory performance and speed up the de-blocking filter, we propose a new architecture for de-blocking filter in H.264/AVC. First we propose a novel filtering order that results in significant saving in both filtering time and local memory usage. And we propose a new data access a method. Let the de-blocking filter can simultaneous access necessity the data in processing process, we can reduce the working cycles. The proposed architecture is synthesized with TSMC 0.13μm technology. The synthesized de-blocking filter architecture could process video in 720P HD (High-definition television, HDTV, 1280×720 pixels/frame, 60 frames/sec video signals) format at 100MHz.
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