Reconfigurable IP of DCT and DWT for image transform coding

• Main Author: 陳毓宏
• Other Authors: Jyh-Jiun Shann
• Format: Others
• Language: zh-TW
• Published: 2008
• Online Access: http://ndltd.ncl.edu.tw/handle/06295153574776263281

碩士 === 國立交通大學 === 電機學院IC設計產業專班 === 97 === This paper presents a design and development of a reconfigurable architecture for image transform coding. Because of DCT (Discrete Cosine Transform) is usually used in JPEG, MPEG, and H.26X system. And DWT (Discrete Wavelet Transform) is used in JPEG2000 system. They are both the part that damage huge computations in system. So we want to integrate DCT and DWT architectures with the same hardware to reduce hardware requirement for these system. To merge DWT into DCT, we use butterfly structure for DCT and 9/7 convolution based structure for DWT that not only can make DCT computations time faster, but also can increase hardware utility rate for DWT. To reduce hardware area and speed up DCT function, we use the subexpression to reduce our hardware requirement and canonic signed digit (CSD) encoded multiplier to design ours multiplication that can effective reduce multiplication area, and also can speed up the chip to achieve the mpeg spec. The architecture executes a DCT and DWT achieving up to 90% higher throughput and occupying as little as 20% area compared to a commercial digital signal processing and other application- specified integrated circuit implementations while maintaining precision. A comprehensive comparative analysis is also provided. The proposed architecture is implemented in 0.13- m CMOS technology and operates with a 100-MHz clock.