| Summary: | 博士 === 國立交通大學 === 光電工程系所 === 97 === This work focuses on the variation behavior of poly-Si TFTs both spatially and temporally. This work is mainly enlightened from, but not limited to, the display electronics. First the spatial variation of the devices is studied for the devices from the mass production line. The serious variation behavior and no description nor trend for the device variation makes it rather difficult for designers to develop the circuits composed of poly-Si TFTs. Thus we referred to the cases in MOSFETs and analogically proposed factors for the variation behavior for poly-Si TFTs. Based on the idea, the special layout called crosstie layout is proposed, measured and the device parameters are extracted and statistically summarized. The feature of the crosstie layout is that the devices are located as close as possible and in such case the long-range variation can be greatly reduced for the two adjacent devices. The device parameters show apparent asymmetric and non-centered distribution, which is much different from the usual Gaussian distribution assumption. A method enlightened from the electronics is proposed to decouple the long-range and micro variation and by finding the difference between the adjacent devices the true micro variation profile can be examined. The micro variation behaviors for the threshold voltage and mobility are found to be more centered and symmetric for both n-type and p-type devices. Two equations are proposed to well fit the micro variation and also based on the models the effects of device variation on the analog and digital circuits are simulated and discussed. In addition, based on the models, the projected device variation behavior for devices with different device dimension is also provided. By utilizing the crosstie layout, the variation behavior of the devices is greatly reduced, take the threshold voltage for instance, from 0.5 V to 0.03 V. The reduced variation also facilitates the following study of temporal variation, in which the effect of spatial variation can be greatly relieved and not to cover the effect of temporal variation.
Then we focus on the temporal variation of poly-Si TFTs under various operation conditions. Here the temporal variation can simply correspond to the reliability issue under DC and AC operation, which would be respectively discussed in the separate chapters. For the DC operation section, we first review the two main degradation mechanisms for the poly-Si TFTs under DC operation, namely the hot carrier effect and the self heating effect. Though there have been so many papers on the device degradation behavior under these two stress conditions, there are very few papers about their capacitance behavior. We study the C-V behavior for the device after the two stress conditions and find that the simulation tool may be incomplete in properly describing the frequency dependence in the C-V curves. Thus we use another approach to infer the C-V curves from the readily-accessible I-V curves. Based on the proposed model composed of the gate insulator capacitance and channel resistance, we compare the magnitude of the capacitance term and the resistance term for the device’s impedance and the critical point called PC is found to help distinguish the ON region and the OFF region in the C-V curves inferred from the I-V curves. Since the capacitance term is dependent on the measuring frequency, the position of the point PC also changes with the measuring frequency. Following the same manner, the C-V behavior for the device after the two stress conditions are examined and the corresponding circuit elements, possibly the capacitance or the resistance, are proposed respectively. Special discussion would be given on the capacitance behaviors for the n-type device after self-heating stress and the p-type after hot carrier stress since they both somehow show the increase of the capacitance for the lower gate voltage in C-V curves.
Next we study the reliability behavior for the device under gate dynamic operation. Started from the application, we find that in TFT-LCD applications the TFTs in the pixels mostly stay in the gate turned-off region with the drain signal dynamically toggling. However, there is almost no study of the reliability behavior on such operation condition. We consider the gate-to-source voltage difference VGS and the gate-to-drain voltage difference VGD and analogically study the reliability behavior for the gate voltage dynamically toggling in the OFF region while the source and drain electrodes are both grounded. The device shows mobility decrease in the I-V curves and shift as well as distortion in its C-V curves for the stressed n-type device, while for the p-type device the mobility increases and the OFF current decreases after stress. The dependency for the device degradation on the pulse parameters, namely the pulse range, the frequency and the duty ratio of the applied signal, is also studied. However, since the pulse voltage is all kept below its threshold voltage, there should be no channel carrier induced beneath the gate electrode and thus the degradation behavior could not be explained by the model proposed previously by Uraoka. At this point we resort to the circuit model again and one more time we discuss the impedance under such stress condition. It is then inferred that under the gate AC operation the channel resistance and the large electric field across the junctions could be the main degraded region. Nevertheless, such inference is hard to probe and we use another test structure named the gated p-i-n device, in which the device has the similar structure to TFTs but one side of the doping is changed to make the device laterally resemble the p-i-n diodes. The feature for adopting such gated p-i-n device is that this device has the similar structure to the TFTs while the channel voltage can be set from one side of the electrodes. Thus, this enables us the capability of forming large electric field across one junction to simulate the condition of gate AC OFF region stress for poly-Si TFTs. Then, by examining the capacitance curves of the AC-stressed TFTs and the DC-stressed gated p-i-n devices after stress, the aforementioned mechanism is verified. The degradation in junction with the large electric field on it is thus found to be responsible for the degradation of gate dynamic operation in the OFF region and the discussion for the different behaviors for the n-type device and p-type device is also provided. Also the reliability behaviors under several other stress conditions are discussed. It is found that, no matter what the carrier source may be the inversion channel carriers, the leakage current or even the inversion channel carriers swept because the gate pulse is to be turned-off, once the large electric filed is across the junction, the carriers would more or less become the hot carrier and result in the similar degradation behavior. In other words, they can be categorized as the “generalized hot carrier effect.” To summarize, the finding of the mechanism as well as the proposed circuit model should provide useful information for the understanding and evaluation of the temporal variation for poly-Si TFTs.
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