| Summary: | 碩士 === 國立成功大學 === 光電科學與工程研究所 === 97 === Implementation of strained-Si MOSFETs with optimum low cost stress-memorization technique for 40nm technology CMOS process was demonstrated. Devices fabricated on (100) substrate with <100> channel orientation provides additional 8% current drivability improvement for strained-Si nMOSFETs without any degradation of pMOSFETs performance. The SMT mechanism was experimentally verified by studying the impact of layout geometry (length of source/drain LS/D, poly spacing LP/P, and gate width W) on the device performance. The SMT devices with LS/D down to 0.11 μm and poly space reduced to 120 nm, no obvious current improvement and more performance degradation is observed compared with control device, indicating that the benefit of stress-memorization technique is substantially eliminated and showing that the SMT-induced stress is originated from the source/drain region in our case.
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