Warpage Simulation of Fan-Out Wafer Level Chip Scale Package

• Main Authors: Shang-Shiuan Deng, 鄧上軒
• Other Authors: Sheng-Jye Hwang
• Format: Others
• Language: zh-TW
• Published: 2009
• Online Access: http://ndltd.ncl.edu.tw/handle/37274369936517085920

碩士 === 國立成功大學 === 機械工程學系碩博士班 === 97 === Wafer level packaging is an important development trend for IC package design. The fan-out wafer level package discussed here has the flip chip form which uses thin-film redistribute then uses solder bump to connect the package to the printed wiring board directly. Liquid compound was used for the encapsulation process. Comparing with wire-bond BGA, the fan-out wafer level package has better electric properties, lower power consumption, and smaller package size. Warpage problem plays an important role in IC encapsulation processes. Previous researchers had focused on warpage analyses with temperature changes between constituent materials and neglected the cure shrinkage effects. However, more and more studies indicate that prediction of warpage according to CTE (Coefficient of Thermal Expansion) was not able to accurately predict the amount of warpage in IC packaging. This paper used mold filling simulation and predicted the amount of warpage considering both thermal and cure induced shrinkage. The liquid compound properties were obtained by various techniques: cure kinetics by differential scanning calorimeter (DSC), cure induced shrinkage by P-V-T-C testing machine. These experimental data were used to formulate the P-V-T-C equation. The P-V-T-C equation was successfully implemented and verified that warpage was governed by both thermal shrinkage and cure shrinkage. The amount of warpage after molding could be accurately predicted with this methodology. The simulation results showed that cure shrinkage of liquid compound was the dominant factor for package warpage after encapsulation. Even after post mold cure, the amount of warpage was still significant.