Fast Algorithms and VLSI Implementations of H.264/AVC Transform-Domain Intra Codec

• Main Authors: Heng-Yao Lin, 林恆瑤
• Other Authors: Bin-Da Liu
• Format: Others
• Language: en_US
• Published: 2009
• Online Access: http://ndltd.ncl.edu.tw/handle/13724757742731242298

博士 === 國立成功大學 === 電機工程學系碩博士班 === 97 === H.264/AVC is the latest digital video coding standard that achieves very high data compression by using several new coding features. In this dissertation, a highly efficient VLSI architecture with macroblock pipeline structure is proposed to increase the coding speed for intra frame codec in H.264/AVC. The major researches include fast implementations of transform-based intra prediction and context adaptive variable length coder (CAVLC). For optimized algorithm and architecture design in intra prediction, a fast mode decision algorithm is represented based on inherent features of discrete cosine transform (DCT). The primary texture direction of the target block can be determined by using the transformed coefficients of the block. Only a few candidate modes are chosen for the cost calculation, which is based on the error model in the sum of absolute integer-transformed differences (SAITD). Experimental results show that the proposed intra prediction algorithm has lower Peak Signal to Noise Ratio (PSNR) degradation and bit-rate increment with the reduction of the coding time by 60% compared to other recent designs. For hardware implementation, the proposed intra prediction algorithm is integrated into intra prediction procedure rather than being a preprocessing units. The residual blocks of the best prediction mode can be obtained directly after the cost generator without re-computing in the intra prediction procedure. In the entropy codec module, the critical path in the CAVLC decoder is first analyzed and then reduced by forwarding the adaptive detection for succeeding symbols. With a shortened critical path, the CAVLC architecture is further divided into two segments, which can be easily implemented by a pipeline structure. Consequently, the overall performance is effectively improved. In the hardware implementation, we suggested two efficient approaches, table partitioning and prefix predecoding, to reduce the unnecessary power consumption in decoding the look up table (LUT) of VLC codes. Moreover, a combined LUT and single output buffer have been adopted to further reduce the area as well as power consumption without affecting the decoding performance. Experimental results show that the proposed architecture surpassing other recent designs can approximately reduce power consumption by 40% and achieve three times decoding speed in comparison to the original decoding procedure suggested in the H.264 standard. Finally, the H.264/AVC transform-based intra codec with TSMC 0.18 μm CMOS technology is realized, where the maximum operation frequency can achieve at 100 MHz, which can easily support the real-time requirements for video resolutions up to the 16 SIF (1408×960) at 30 frames/sec video format.