A High-Speed Pipelined Analog-to-Digital Converter Using Wide-band Sample-and-Hold Amplifier

• Main Authors: Tz-Jing Shau, 邵姿菁
• Other Authors: Soon-Jyh Chang
• Format: Others
• Language: en_US
• Published: 2009
• Online Access: http://ndltd.ncl.edu.tw/handle/11783467475044626175

碩士 === 國立成功大學 === 電機工程學系碩博士班 === 97 === With the advance of deep submicron technology, the low supply voltage will become the trend of circuit development due to the device’s reliability issues. However, the signal dynamic range will be decreased because of the reduction of supply voltage. In order to maintain the dynamic range, the noise and signal distortion must be suppressed. By this way, it will indirectly increase the power consumption of analog circuits. Especially, a high-gain op-amp is necessitated to guarantee the required accuracy in the conventional pipelined ADC. However, due to the process limitations, it is difficult to implement such a high-gain op-amp. The penalty of additional power dissipation must be paid to implement this op-amp. In this thesis, a technique called as wide-band folded SHA is proposed to relax the requirement of high-gain op-amp and increase the tolerable input swing in a pipelined ADC. A 10-bit 200 MS/s pipelined ADC with the proposed wide-band folded SHA has been designed with the TSMC 0.18 �慆 CMOS 1P6M process to demonstrate the effectiveness of the proposed SHA.