Efficient Software-Based Self-Test Methods for Embedded Digital Signal Processors

• Main Authors: Jun-Jie Zhu, 朱俊杰
• Other Authors: Ming-Der Shieh
• Format: Others
• Language: zh-TW
• Published: 2009
• Online Access: http://ndltd.ncl.edu.tw/handle/11171110539671036352

碩士 === 國立成功大學 === 電機工程學系碩博士班 === 97 === With rapid development of SoC (System-on-Chip) techniques, dual core processors (ARM and DSP processor) are extensively used in consumer electronics like mobile phone, digital camera, etc. Since the embedded processor plays an important role in SoC, an efficient test method with little overhead and high fault coverage has become a critical issue. Compared with the scan-based test methods, the software-based self-test (SBST) method does not suffer from area overhead and performance degradation, and can provide at-speed test for DSPs with the potential drawbacks of lower fault coverage and a larger amount of test vectors. This work first presents a DSP processor designs based on TMS320C54x series. Then we propose a hybrid software-based test method for the developed DSP. In the developed SBST method, techniques such as the constrained ATPG, random/pseudorandom patterns, and specific templates for the instruction set architecture are employed to enhance the fault coverage of the DSP core. Experimental results exhibit that applying the developed SBST test flow obtains more than 96% fault coverage for our DSP core, which is higher than the reported values in related works.