| Summary: | 碩士 === 國立成功大學 === 電機工程學系碩博士班 === 97 === Due to the rapid progress in IC design and development, the number of integrated IP cores in SOC designs is increasing, and the communication between IP cores are increasing accordingly. However, the traditional bus design is out-of-date to deal with the large amount of communication data, and the communication architecture becomes one of the bottlenecks of system performance of System-on-Chip (SOC) designs. As a result, it is a critical design issue about how to develop advanced bus architecture to satisfy the high performance requirements and improve the overall performance of SOC designs.
Moreover, many of the cores in SOC designs come from different designers or vendors who have different communication interfaces. Therefore, the bus design should not only be flexible and reusable but also easy to be integrated with other IP designs. The bus interface plays an important role in determining the efforts of system integration, so it is efficient to ease the complex integration flow by adopting standard protocols of interface for bus models for bus models. Open Core Protocol (OCP) is an freely available and on-chip interconnect independent interface standard, which provides flexible, scalable and configurable interfaces design to match the communication requirements associated with different IP cores and achieve the goal of “Plug and Play.” OCP further reduce the effort of system integration and increase the reusability of IP as well.
In this thesis, we focus on: 1) develop the high performance bus design which supports several advanced transfer functionalities, 2) providing the flexible transaction level bus models having OCP standard interface with high simulation speed, and 3) implementation of RTL models for complete design and verification procedure. We proposed the full-crossbar or partial-crossbar high performance bus architecture with OCP standard interfaces.
The proposed bus model adopts the OCP standard for bus interfaces to shorten integration time. It supports the multi-master to multi-slave arbitration scheme and several advanced communication features including parallel, pipeline, burst, multiple outstanding and out-of-order transactions. Especially, the out-of-order transaction allows the SOC system re-scheduling the responses, such that the latency of transactions is decreasing and the bus throughput and system performance are improved. Besides, the parameterized bus design is flexible. System developers are able to adjust the parameters to select the suitable system configuration to meet the performance requirements of various applications of systems. The simulation results show that the proposed bus design reduces the long transaction latency efficiently and further improves overall system performance.
|
|---|
