| Summary: | 碩士 === 國立成功大學 === 航空太空工程學系碩博士班 === 97 === Abstract
Along with advance in technology, Flip Chip has the tendence toward lower profile, lighter weight, and higher density. Due to the mismatch of the coefficients of thermal expansion (CTE) between the chip and substrate, the solder joints tend to fail under high thermal stresses. In order to enhance the reliability of the solder joints, underfill encapsulation is filled into the gap between the chip and substrate around the solder joints by capillary force. The underfill encapsulant is used to decrease the CTE mismatch between chip and substrate. However, the underfill flow is very slow and could be incomplete, leading to the generation of voids. Therefore, it is crucial for flip-chip technology to speed up the encapsulation process and avoid the formation of voids at the same time. In this study, we will compare the result of underfill experiments with the simulations, The behaviors of filling in different bump design model be studied. A systematic method is also proposed to construct the underfill schedule.
Key word : Flip Chip Encapsulation，Underfill，Capillary，Edge Effect，Bump Pitch
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