| Summary: | 博士 === 國立成功大學 === 工程科學系碩博士班 === 97 === To evaluate conjointly the effects of ambient temperature fluctuation and operation bias on the reliability of board-level electronic packages, a coupled power and thermal cycling test has been proposed by JEDEC. In this study, thermal characteristics of a board-level chip-scale package subjected to coupled power and thermal cycling test conditions are first investigated through the transient thermal analysis. Tabular boundary conditions are utilized to deal with time-varying thermal boundary conditions brought by thermal cycling. The numerical model was successfully calibrated using steady-state and power cycling experiments.
The sequential thermal-mechanical coupling analysis, which solves in turn the transient temperature field and subsequent thermomechanical deformations, is performed to investigate thermal characteristics along with fatigue reliability of board-level single-die and stacked-dies thin-profile fine-pitch ball grid array (TFBGA) chip-scale packages under coupled power and thermal cycling test conditions. Effects of different power cycling durations and sequences are studied. A pure power cycling and a pure thermal cycling condition are also examined and compared.
For the thermal characteristics, it is obvious form the analysis that the presence of power cycling leads to a significant deviation of the junction temperature from the thermal cycling profile. However, for components away from the die, though the patterns of temperature histories are similar, the temperature excursions are less significant. Moreover, for low-power applications, temperature histories from coupled power and thermal cycling are approximately linear combinations of temperature histories from pure power cycling and the ones from pure thermal cycling.
Thermomechanical reliability prediction indicate that, for the coupled power and thermal cycling test on board-level single-die TFBGA’s, a shorter power cycling duration in general leads to a shorter fatigue life. However, the temperature compensation effect elongates the fatigue life under certain power cycling durations. For the board-level stacked-dies TFBGA’s, reliability performances of a board-level stacked-die package should be similar as long as the total power dissipation prescribed to the package is identical, regardless of how the power distributes among separate dies.
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