Architecture Design of H.264 Discrete Cosine Transform
碩士 === 國立成功大學 === 電機工程學系碩博士班 === 97 === This thesis proposes a Discrete Cosine Transform architecture with high throughput and low area. This architecture can be applied in H.264 High Definition (HD) resolution video products. In H.264, the block sizes of the Discrete Cosine Transform are 4×4 and 8×...
Main Authors: | Yen-Long Hsieh, 謝顏隆 |
---|---|
Other Authors: | 李國君 |
Format: | Others |
Language: | en_US |
Published: |
2009
|
Online Access: | http://ndltd.ncl.edu.tw/handle/74024470056539167481 |
Similar Items
-
An Efficient VLSI Architecture for Inverse Quantization and Inverse Discrete Cosine Transform in H.264/AVC FRExt
by: Sheng-Tsung Hsu, et al.
Published: (2007) -
Architecture Design for Video Deccoder and Discrete Cosine Transform
by: Lee, Yung-Pin, et al.
Published: (1997) -
A Parameterizable Architecture for Two-Dimensional Discrete Cosine Transform and Inverse Discrete Cosine Transform
by: Hsing-Juan Tsai, et al.
Published: (2005) -
Distributed arithmetic architecture for the discrete cosine transform
by: Poplin, Dwight
Published: (2012) -
Design and Implementation of Discrete Cosine Transform
by: Chingson Chen, et al.
Published: (1995)