| Summary: | 碩士 === 國立成功大學 === 電機工程學系碩博士班 === 97 === This thesis proposes a Discrete Cosine Transform architecture with high throughput and low area. This architecture can be applied in H.264 High Definition (HD) resolution video products. In H.264, the block sizes of the Discrete Cosine Transform are 4×4 and 8×8. The 8×8 block size transform is mainly used in Standard Definition resolution, High Definition resolution, and above Definition resolution. This thesis implements an 8×8 transform architecture. For application in HD resolution video products, the proposed architecture supplies enough high throughput, but a big area should also be associated with a high throughput. Through some property of the DCT, this thesis shows that the area can be reduced and then a high
throughput and small area architecture can be implemented.
In the proposed architecture, the specification of proposed architecture is 1080p and 60 frames per second. The proposed architecture is synthesized with
TSMC 0.18 μm technology cell library and the operating speed is 81 MHz. In this operation speed, the proposed architecture has smaller area when compared with other
architectures which also implement H.264 8×8 DCT architecture recently.
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