Design of a 6 Bits 1GS/s Digital to Analog Converter

• Main Authors: Chia-Hung Lin, 林佳鴻
• Other Authors: Wei-Liang Lin
• Format: Others
• Language: zh-TW
• Published: 2008
• Online Access: http://ndltd.ncl.edu.tw/handle/58479793936563974203

碩士 === 國立中興大學 === 電機工程學系所 === 97 === This thesis designs a 6-bit 1GS/s Digital-to-Analog Converter (DAC). The DAC uses full thermometer-coded current steering architecture. In order to degrade the mismatch between the transistors in the current source, we discuss about the size design of the current transistor. And we discuss how to make the DNL and INL to reach below 0.1 LSB. Gradient-induced mismatch errors are compensated by using a quadrant centro-symmetric layout. It uses TSMC 0.35 um standard CMOS technology, the supply voltage is 3.3 V. DNL is about ±0.1 LSB, INL is about ±0.3 LSB. When clock in = 10M, the spurious-free dynamic rang (SFDR) of 21.31 dB can be achieved with 1M digital sine input, and the total power dissipation is 35.2 mW.