| Summary: | 碩士 === 國立中興大學 === 電機工程學系所 === 97 === Low-Density Parity-Check (LDPC) codes are one of the best error correcting codes that enable the future generations of wireless devices to achieve higher data rates. This thesis presents a high throughput, parallel, scalable and irregular LDPC decoding system hardware implementation that supports twelve combinations of block lengths 648, 1296 and 1944 bits and coding rate 1/2, 2/3, 3/4 and 5/6 based on IEEE 802.11n standard.
Our proposed LDPC decoder is a parameterize IP core running the well-known TDMP and SMSA decoding algorithm. The decoder works in pipeline, very effective technique to rearrange the sequence of its elaborations is proposed in order to minimize the iteration latency, and our proposed reducing switch activity algorithm reduces active node switching activities to lower LDPC decoder power consumption. Layered nodes are periodically refreshed to minimize coding gain degradation. Moreover, we further improved the design with pipeline structure, parallel computation and no memory unit. Therefore, we can decode six different codewords at same time and only use one routing network to route data.
The prototype architecture is being implemented on several VLSI technologies (TSMC 0.18 um and UMC 90 nm) and tested on the Xilinx Virtex-5 (XC5VLX330) FPGA. The proposed multi-rate LDPC decoder has the following advantages when compared to recent state-of-the-art architectures: (1) fully support IEEE 802.11n specification (20/40 MHz); (2) smaller normalized area about 66% in average; (3) reduced about 26% normalized energy.
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