Investigation of Degradation Mechanism of CLC n-TFTs under High Field and Temperature Stress

• Main Author: 江品姓
• Other Authors: 王木俊
• Format: Others
• Language: zh-TW
• Published: 2009
• Online Access: http://ndltd.ncl.edu.tw/handle/87489852698582973634

碩士 === 明新科技大學 === 電子工程研究所 === 97 === Recently, low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs) have been the trend of active matrix display driving circuitry. These devices unavoidably show more serious degradation of device performance in BTI (BTI) stress than in hot-carrier stress (HCS). In this study, the proposed TFT channel was fabricated with continuous-wave (CW) green laser-crystallization (CLC) conquering the barrier of the hardly controlled pulse-to-pulse repeatability (PPR) and implementing the possibility of large-area panel of poly-Si TFT, and the degree of crystallization increases of channel layer by CW laser. The gate dielectric was deposited of TEOS-SiO2 with a 100-nm thickness by plasma enhanced chemical vapor deposition (PECVD). The defect generation of CLC poly-Si TFT under high gate-voltage stress and temperature impact was firstly investigated. The PBTI stress was performed at the temperature range varied from 25 ℃ to 125 ℃ and the stress gate voltages were 18V and 20V with the source and drain grounded. From the experimental results, the degradation mechanism of device performance in CLC poly-Si TFT under two stress conditions and various laser anneals was chiefly caused by the surface interface between gate oxide and channel poly-Si, especially dissolving Si-H+ bonds or producing the interface states. Furthermore, since the laser anneal energy was raised, the PBTI degradation was slightly improved.