Yield Study to Backend Wafer Level Assembly

碩士 === 明新科技大學 === 電子工程研究所 === 97 === The die size and the thickness of IC substrate always change due to the different market requirements while the semiconductor process and the product applications develop fast. In order to satisfy the market concerns, the improvement of wafer grinding and dic...

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Main Authors: Huang Kuo Shu, 黃國書
Other Authors: 王木俊
Format: Others
Language:zh-TW
Published: 2009
Online Access:http://ndltd.ncl.edu.tw/handle/04832821610754694701
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spelling ndltd-TW-097MHIT54280082015-11-16T16:09:09Z http://ndltd.ncl.edu.tw/handle/04832821610754694701 Yield Study to Backend Wafer Level Assembly 晶圓級IC封裝之良率提升研究 Huang Kuo Shu 黃國書 碩士 明新科技大學 電子工程研究所 97 The die size and the thickness of IC substrate always change due to the different market requirements while the semiconductor process and the product applications develop fast. In order to satisfy the market concerns, the improvement of wafer grinding and dicing saw technology is necessary to provide lighter, thinner and more reliable ICs. Generally, most of previous commercial ICs almost showed the square profile, but liquid-crystal-display (LCD) driver ICs demonstrate approximate rectangle shape. Furthermore, the ratio of length / width is near 14:1, therefore, it’s easy to be broken during IC assembly process and induce some reliability defects. As the latest of IC stack process, wafer thickness is only 30um, package thickness is 1.4mm within 16ea chips. Therefore we need strong process to satisfy different requirement of IC assembly. Recently, the cutting technology cardinally relies on the thinner diamond blade plus some variable dicing saw parameters to obtain the separate chips. In present species of cutting machine, except some advanced products or special wafers with laser cut method, most of commercial ICs are still cut with single-cut machine. During dicing saw, the considerable dirty water can make serious pollution on bond pad、solder bump or gold bump, finally the quality of end process is unreliable. The immunity capability of electrostatic discharge (ESD) at sub-micron or below complementary meta-oxide-semiconductor (CMOS) ICs is falling down, therefore the ESD in dicing saw is a critical issue. In this study, we investigate the recent wafer cutting methods and how to enhance strength of wafer also protect the pad quality in ICs and prevent ESD damaged. During this effort, we expect that one is to increase the grinding and cutting process yield; the other is to practically reduce the assembly-line cost. 王木俊 2009 學位論文 ; thesis 73 zh-TW
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language zh-TW
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description 碩士 === 明新科技大學 === 電子工程研究所 === 97 === The die size and the thickness of IC substrate always change due to the different market requirements while the semiconductor process and the product applications develop fast. In order to satisfy the market concerns, the improvement of wafer grinding and dicing saw technology is necessary to provide lighter, thinner and more reliable ICs. Generally, most of previous commercial ICs almost showed the square profile, but liquid-crystal-display (LCD) driver ICs demonstrate approximate rectangle shape. Furthermore, the ratio of length / width is near 14:1, therefore, it’s easy to be broken during IC assembly process and induce some reliability defects. As the latest of IC stack process, wafer thickness is only 30um, package thickness is 1.4mm within 16ea chips. Therefore we need strong process to satisfy different requirement of IC assembly. Recently, the cutting technology cardinally relies on the thinner diamond blade plus some variable dicing saw parameters to obtain the separate chips. In present species of cutting machine, except some advanced products or special wafers with laser cut method, most of commercial ICs are still cut with single-cut machine. During dicing saw, the considerable dirty water can make serious pollution on bond pad、solder bump or gold bump, finally the quality of end process is unreliable. The immunity capability of electrostatic discharge (ESD) at sub-micron or below complementary meta-oxide-semiconductor (CMOS) ICs is falling down, therefore the ESD in dicing saw is a critical issue. In this study, we investigate the recent wafer cutting methods and how to enhance strength of wafer also protect the pad quality in ICs and prevent ESD damaged. During this effort, we expect that one is to increase the grinding and cutting process yield; the other is to practically reduce the assembly-line cost.
author2 王木俊
author_facet 王木俊
Huang Kuo Shu
黃國書
author Huang Kuo Shu
黃國書
spellingShingle Huang Kuo Shu
黃國書
Yield Study to Backend Wafer Level Assembly
author_sort Huang Kuo Shu
title Yield Study to Backend Wafer Level Assembly
title_short Yield Study to Backend Wafer Level Assembly
title_full Yield Study to Backend Wafer Level Assembly
title_fullStr Yield Study to Backend Wafer Level Assembly
title_full_unstemmed Yield Study to Backend Wafer Level Assembly
title_sort yield study to backend wafer level assembly
publishDate 2009
url http://ndltd.ncl.edu.tw/handle/04832821610754694701
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AT huángguóshū jīngyuánjíicfēngzhuāngzhīliánglǜtíshēngyánjiū
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