| Summary: | 碩士 === 華梵大學 === 電子工程學系碩士班 === 97 === This thesis studies the design of iterative learning controllers for discrete time nonlinear system, and uses a type-2 fuzzy logic system to adjust the learning gain of the proposed controller. As the membership function of type-1 fuzzy set must be an exact function, the type-1 fuzzy logic system can not be applied if there exist some uncertainties for the membership functions. It will be suitable to use the type-2 fuzzy logic system for the design of fuzzy learning gain since the construction the membership function for learning gain is also difficult. Hopefully, the type-2 fuzzy learning gain can overcome the design uncertainties and improve the learning performance. This thesis also analyze the convergence behavior of the iterative learning system. It is shown theoretically that the stability and convergence can be guaranteed if the fuzzy learning gain satisfies certain sufficient condition. In addition, the convergent speed and the average learning error of type-2 fuzzy iterative learning controller are shown to be better than those of type-1 fuzzy iterative learning controllers by computer simulations.
In addition to the computer simulations by Matlab, the proposed type-2 fuzzy iterative learning controllers is also realized by a digital circuit. The designed circuit consists of four parts, including control unit circuit, register circuit, type-2 fuzzy logic learning gain circuit and iterative learning control circuit. We use VHDL to implement the circuit on an FPGA chip. In order to verify the correctness of the circuit, we utilize a hardware interface of DIO card to connect the FPGA chip and the personal computer such that we can execute the closed loop control experiment. Compared with the Matlab simulation results, we conclude that the designed circuit is correct and feasible.
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