| Summary: | 碩士 === 大葉大學 === 電信工程學系碩士在職專班 === 97 === A remote telemetry system consists of a computer and a field programmable gate array (FPGA) platform. This study is to design a FPGA-based architecture of the telemetry communications platform. Far end telemetry remote sensors detect signals and sent them to the computer system via data transmission media. Then, the signals are converted to PCM parallel format by means of multiplex signal processing. Finally, the FPGA platform converts the parallel PCM signals to a bit stream through frame synchronization. In order to reduce the transmission bandwidth and to concentrate power in the baseband signal to improve the transmission efficiency, the bit stream pass through a low-pass filter to form a rounded square wave. Such sine wave-like bit stream modulates the intermediate frequency (IF) and increase frequency to radio frequency (RF), and transmit to near end.
In the near end, the re-distorted signal of bit stream caused by the transmission media, have to rebuild the signal to form a normal square wave. The reconstruction work is to be served by the bit synchronizer and the FPGA platform’s frame synchronizer recovers the individual measurement parameters which are measured by remote end. Then, distributors pass the measuring data to the computer for data processing and display applications. Therefore, the system is a combination of front-end of data acquisition hardware and back-end of data processing and display software of the communication platform.
Although today's computers have enormous computing ability, but based on the benefit of which to reduce the time of computing process as well as the delay time due to multiplex process of computer tasking. Utilizing the advantages of FPGA’s attributes of concurrent, real-time processing capability of hardware, single task, the majority of processing units were transplanted to the FPGA platform. The FPGA efficiently performs data synchronizations and decoding operations. In addition to, using PCI interface DMA (Direct Memory Access) transfer mode can be done for high-speed IO channels between computer and FPGA.
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