| Summary: | 碩士 === 大葉大學 === 電機工程學系 === 97 === In this study, soft decision decoding of Viterbi algorithm is written with very high speed integrated circuit hardware description language(VHDL) on a micro-cpu design. A simple 16-bit processor has been modified to a 32-bit processor, which the addition and multiplication of IEEE single precision floating-point numbers are included. This designed 32-bit processor is specified to perform a Viterbi algorithm. An example of (2,1,3) convolutional decoding with length 300 is illustrated to verify such a micro-cpu design. A synthesis software, Synplify pro, is employed to synthesize such a proposed circuit design. There is a comparison listed to compare LUTs difference between Virtex-II Pro and Virtex-5.
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