| Summary: | 碩士 === 大葉大學 === 電機工程學系 === 97 === The thesis of this research is taken the advantages on design a Multi-processor structures. The processor core is the structure function like PIC which is proposed by this research. After this design, we expect this processor core can interconnect add the network in order to get good compromise policy.
The produce of this thesis is using Verilog or VHDL hardware describe language to produce like PIC core first, and then use ModelSim and SynaptiCAD software to simulate the correction of PIC core. After interconnecting networks analysis and test, the results of simulation will show that the idea is correct.
The purpose of this research is not only to design more than one multi-core-cpu actually, discuss how good of multi-core-structure performance, but also find the problem of core and core communications and attempt to improve the efficiency of the whole multi-core-structure.
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