ANALYSIS AND IMPROVEMENT OF INSERTED AND BUTTING SUBSTRATE PICKUP LAYOUT STYLE IN ESD NMOS DEVICES

• Main Authors: Po-Kuan Sung, 宋柏寬
• Other Authors: 黃至堯
• Format: Others
• Language: en_US
• Published: 2008
• Online Access: http://ndltd.ncl.edu.tw/handle/63653979465602026546

碩士 === 清雲科技大學 === 電子工程系所 === 97 === In multi-finger ESD NMOS, the butting or inserted layout of the substrate/well pickups of MOSFETs strictly degrades ESD robustness owing to the substrate resistance shorting effect. Therefore, this thesis studies on this layout restriction issue in detail. Extrinsic well/diffusion resistance insertion between the NMOS substrate body and ground can greatly improve the ESD performance degradation. Hence, we design eight types of the NMOS multi-finger layout plots, in order to obtain related mechanism parameters and hence improve ESD performance. In the simulation part, we focus on the butting/inserted NMOS structure, and comparing to the gate-grounded NMOS. The analysis results imply that butting/inserted substrate pickup leads to small substrate resistance, so that the parasitic NPN BJT can hardly turn on, and thus reduce the ESD robustness of the NMOS device.