| Summary: | 碩士 === 中原大學 === 醫學工程研究所 === 97 === In recent years, medical image systems utilize high resolution pixels to express body tissue structures. The huge amount image processing requirement became a burden to most general purpose computer system. In this study, an FPGA-based, scalable number crunching system is built to realize high-speed medical image processing applications.
To simplify the implementation of medical image processing applications, the system provides varieties image processing intellectual properties (IP). These IP libraries provide optimized processing algorithms and shorten the timeline to construct an image applications. The embedded microcontroller in the FPGA is also used to coordinate the integrated image processing paradigms and to realize the embedded high speed medical image processing system.
To verify and validate the system, a mammogram processing application is implemented. The algorithms, stepwise development and hardware co-simulation procedures are comprehensively described. The performance comparisons by the general purpose CPU system and the FPGA based system are also presented
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