The Study of CMOSFET Performance Fabricated on Hybrid Orientation Substrates

• Main Authors: Kuo, Chia-Ming, 郭家銘
• Other Authors: 康定國
• Format: Others
• Language: zh-TW
• Published: 2009
• Online Access: http://ndltd.ncl.edu.tw/handle/30623618314988152866

碩士 === 正修科技大學 === 電子工程研究所 === 97 === We utilize hybrid orientation technique (HOT), i.e., wafer bonding and selective epitaxy, to fabricate CMOSFET. The HOT CMOSFET consists of nMOSFET grown on (100) plane and pMOSFET grown on (110) plane. Thus, (110) pMOSFET has a great improvement in drive current, whereas (100) nMOSFET has a less influence on drive current. In the thesis, we employ these different surface treatment conditions to improve the oxide interface quality because the selective epitaxy technique is applied to form (100) nMOSFET. Furthermore, when the oxide thickness is reduced, the low-voltage tunneling current measurement can respond to the difference in the oxide interface quality between the surface treatment conditions and further point out the optimum process condition. Besides, for (110) pMOSFET there are two different channel directions, i.e., <110> and <100>. The two channel directions also appear to be different drive current. Thus, we would like to measure the impact ionization efficiency (IIE) in (110) pMOSFET. For a long channel pMOSFET, the IIE in (110)/<110> is greater than that in (110)/<100>. This result can is mainly attributed to the reduced threshold energy for impact ionization. Especially for a short channel pMOSFET, the IIE difference between (110)/<110> and (110)/<100> appear to be negligible. This cause could be reasonably explained by the velocity overshoot effect.