A Study of High-Resolution All-Digital Phase-Locked Loop
碩士 === 中華大學 === 電機工程學系(所) === 97 === The quality of parallel synchronization signal in communication systems is very important. Therefore, Phase-Locked Loops (PLLs) are common circuits of modern circuit design. Traditionally, a Phase-Locked Loop is making up of an analog circuit. The analog-PLL (APL...
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2009
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| Online Access: | http://ndltd.ncl.edu.tw/handle/10104992573991641021 |