A Study of High-Resolution All-Digital Phase-Locked Loop

• Main Authors: Kuan-Chieh Chao, 趙冠傑
• Other Authors: 許騰仁
• Format: Others
• Language: zh-TW
• Published: 2009
• Online Access: http://ndltd.ncl.edu.tw/handle/10104992573991641021

碩士 === 中華大學 === 電機工程學系(所) === 97 === The quality of parallel synchronization signal in communication systems is very important. Therefore, Phase-Locked Loops (PLLs) are common circuits of modern circuit design. Traditionally, a Phase-Locked Loop is making up of an analog circuit. The analog-PLL (APLL) has good quality of phase noise and loop bandwidth. But, the APLL is sensitive to process, supply voltage and temperature. The current trend is towards All-Digital Phase-Locked Loop (ADPLL). In this study, we proposed an ADPLL. The minimum resolution of Digital Controlled Oscillator (DCO) is the major concern of this thesis. The proposed DCO used AOI/OAI standard cells to form as digitally controlled varactor (DCV). Base on the technology of DCV, the minimum resolution of DCO is 10fs. By Spice simulations, the operation range of this DCO is between 0.66MHz and 530MHz.