| Summary: | 碩士 === 長庚大學 === 電機工程學研究所 === 97 === Power systems compensated by static synchronous compensator (STATCOM) is superior to the conventional fixed capacitor because of dynamic reactive power compensation and smaller volume/weight due to high integration of semiconductor structure. This thesis presents a FPGA-based harmonic elimination pulse-width modulated STATCOM to suppress lower order harmonics and to limit switching losses for high power applications. In the developed approach, the off-line computations of switching patterns based on harmonic elimination strategy are stored in EPROM, thereby allowing a microprocessor-free design. Furthermore, in order to simplify the control system and to reduce the system cost, the ac and dc voltage regulators were proposed in place of the current regulators. A droop control strategy was adopted to minimize the error bound caused by uncertainty in source impedance and therefore large change in control output due to small deviation in load voltage can be avoided. The validity of the proposed control algorithm has been verified by laboratory experiments on a 2.5kVA DSP-based controlled prototype. The experimental results for the steady-state operating condition and transient operating condition for the system subjected to various step load changes, which include inductive load and capacitive load, are presented to demonstrate the effectiveness of the proposed controller.
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