| Summary: | 碩士 === 國立中正大學 === 通訊工程研究所 === 97 === Since the performance of LDPC codes is very close to Shannon limit, the related work has been widely discussed in the field of channel codes. Now, the reduction of the computation complexity in the iterative decoding algorithm for LDPC codes has become an essential issue. The decoding procedure of the Quasi-Cyclic (QC) LDPC code, one of LDPC code class, is suitable for parallelism with the feature of parity check matrix. This parallel decoding strategy can maintain the similar capability of error correction. Consequently, the memory utilization is optimized with the modified Min-sum algorithm in the QC-LDPC decoder.
In traditional decoder design, check-to-variable messages and variable-to-check messages are separately stored in the memory, and the decoder consists of the Check Node Function Units (CNFUs) and the Variable Node Function Units (VNFUs). However, this design is memory consumption. In order to overcome this drawback, we propose an efficient architecture to reduce the cost of memory. The storage of all check-to-variable messages in a row of parity check matrix is organized as a efficient chunk. For the required check-to-variable messages in VNFU, the recover unit regains corresponding ones. After variable-to-check messages being updated by VNFU, it won’t be stored in memory directly; instead we use variable-to-check messages to update the efficient chunk that is used by the predictor in the next iteration. Without storing all check-to-variable messages and variable-to-check messages in the memory, this decoding architecture only stores several efficient chunks. So the cost on memory is less.
In our experimental result for the regular QC-LDPC code, this novel strategy can save memory about 65%, compared to the traditional one.
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