| Summary: | 碩士 === 國立中正大學 === 資訊工程所 === 97 === As the number of cores in a chip is increased, several new designs of memory system have been created. Based on Single-Cycle Ring interconnection offers several advantages for hierarchical clustering in future many-core systems, in terms of cost, latency, and power reductions. Moreover, based on the proposed SC_Ring, this work realizes a "level-1 non-uniform cache architecture" (L1-NUCA) for fast data communication without cache-coherency in facilitating multithreading/multi-core. The design strategy of no cache-coherency is that the address space is partitioned by the proposed MMU (memory management unit) as private, shared, and non-cacheable space. The shared address space is distributedly mapped to L1 data caches by the cores’ data locality in the same cluster (so-called L1-NUCA), and the non-cacheable addresses will directly access the L2-NUCA for communicating with other clusters. And we discuss different strategies in our NUCA design to obtain more performances and reduce more power consumption. Finally, experimental results show that our approach yields promising performance.
At this time, power consumption is an urgent challenge. In this paper, we will compare the power consumption with MESI cache-coherency protocol and migration strategies.
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