FPGA Implementation of a Tap-Selective Maximum Likelihood Channel Estimator Equipped with Minimum Description Length Criteria

• Main Authors: Hung-Ta Chan, 詹鴻達
• Other Authors: 黃正光
• Format: Others
• Language: zh-TW
• Published: 2008
• Online Access: http://ndltd.ncl.edu.tw/handle/53465622209531531547

碩士 === 元智大學 === 通訊工程學系 === 96 === In sparse multipath channels a tap-selective maximum likelihood (TS-ML) channel estimation algorithm is proposed for long-range broadband block transmission system. In this paper, we use low complexity TS-ML criterion in the Channel Estimator , it include IFFT calculation block, channel tap power calculation block, sorting block, MDL2 criterion block, we get the number of significant channel taps by use these blocks, final we use number of significant channel taps and channel power descending order to get channel estimation value. In this paper we focus FPGA implementation of a Tap-Selective Maximum Likelihood channel estimator equipped with Minimum Description Length Criteria. Under Xilinx XtremeDSP Virtex-4 FPGA platform we design circuit of TS-ML channel estimator. There are three stages in verification, first we get channel estimation value by using Matlab simulation, then we also get channel estimation value by using Xilinx simulation , final we download simulation result of Xilinx in FPGA board and get channel estimation value by logical analyzer, we also compare the channel estimation value by using these three stages, the result of hardware implementation approach to simulation by computer, and the accuracy of channel estimation is very good