| Summary: | 碩士 === 元智大學 === 資訊工程學系 === 96 === To achieve minimum signal propagation delay, the non-uniform wire width routing architecture has been widely used in modern VLSI design. The non-uniform routing architecture exploits the wire width flexibilities to trade area for performance. However, many additional design rules, which confine the routing flexibilities, are introduced in nanoscale circuit designs. With the increasing difficulties of fabricating nanoscale circuits, the conventional non-uniform routing architecture becomes clumsy. We propose an uniform dual-rail routing architecture to cope with these new challenges. The simulation results demonstrate that our proposed architecture provides a signal propagation channel with similar propagation delay, less crosstalk noise, and less power consumption to the conventional non-uniform routing architecture with moderate routing area overheads. Furthermore, we implement the dual-rail routing architecture in the prefabricated design style and propose a dual-rail algorithm to reduce routing track overheads. The experimental results demonstrate that our proposed techniques successfully trade the track overheads for the interconnect delay.
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