| Summary: | 碩士 === 元智大學 === 資訊工程學系 === 96 === Nowadays is a digital life, to success this goal we must use digital signal process’s algorithm to transform analogy signal to digital signal. Which fast fourier transforms (FFT) play an important role in orthogonal frequency division multiplexing (OFDM) based communication system.
FFT is a fast algorithm of discrete foruier transform (DFT), using radix-2 butterfly unit to be a basic computing module to complete N-point FFT computation. In the present thesis, performance and flexible are considered, and 8-point FFT are used to be a basic process element to construct N-point FFT architecture. The control unit will decide which butterfly unit in different level requires twiddle factor’s address and data path. Then cooperate with data address generation to get corresponding computing data address. Follow this method will reach computing flexible and improve performance.
In the present thesis, we use the Verilog HDL within Xilinx ISE 9.1i design tool to complete this architecture. After that, we use FPGA for function simulation and verify computation data, and the result will be compared with FFT result within Matlab. At the end we will discuss the effect of this architecture result’s precision after continue multiplier and adder.
|
|---|
