Architecture Design and Implementation of Modified Collapsed CORDIC Algorithm

• Main Authors: Kuo-Zeng Wu, 吳國正
• Other Authors: Chuen-Yuan Chen
• Format: Others
• Language: zh-TW
• Published: 2008
• Online Access: http://ndltd.ncl.edu.tw/handle/3j66b7

碩士 === 國立雲林科技大學 === 電機工程系碩士班 === 96 === In this thesis, we implement the sine/cosine function generator based on the modified collapsed CORDIC algorithm. In the architecture with N-bit precision, the computations in the first N/3 stages are simply realized by a look-up table while the computations in the remaining stages are realized by a series of shift-and-add operations.We take advantage of the concepts of Canonic Signed Digit Representation, Tree Height Reduction Technique, Two’s Complement Representation, and Carry Lookahead Adder to design the related functional blocks. In addition, the pipelined architecture is adopted to improve the operational speed. For the hardware implementation, the whole design are simulated with Modelsim and verified with Xilinx ISE developing system. The experimental results from Xilinx V4IP-1000 show that the operational speed of this design can be up to 126.31 MHz.