An All Digital Pulsewidth Locked Loops Using Recyclable Sampling Detection Technique
碩士 === 國立雲林科技大學 === 電子與資訊工程研究所 === 96 === In the high-speed digital system chip, the quality demand of clock signals are more and more strictly. Except clock phase, a robust and controllable pulsewidth is also getting important. Generally, the high-speed pulsewidth control loops (PWCL) has mixed sig...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2008
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| Online Access: | http://ndltd.ncl.edu.tw/handle/8878bt |