| Summary: | 碩士 === 淡江大學 === 電機工程學系碩士班 === 96 === With the extensive growth of the demand for high speed system, the required clock rate continues increasing. Thus, the issue of the clock synchronization among IC modules becomes more and more important, which results in a great improvement on the clock skew buffer and the data link technology. Though the Phase-locked loops (PLLs) provides a well locking loop for the clock synchronization, its inherent high-order loop and jitter accumulation nature make the high-accuracy PLL design difficult. On the other hand, the Delay-locked loops (DLLs) become more favourable than the PLL recently due to its no jitter accumulation in VCDL. DLLs are widely used in wireless telecommunications, such as wireless local area net-works (WLANs), mobile and satellite communications. DLLs and PLLs play an important role in the phase locked and the clock synchronization.
With the characteristics of stability and no noise accumulation, the DLL is more widely used than PLL in many applications, such as Time Recovery and Local Oscillator, which makes the DLL more and more important. However, there are still some disadvantages existing in traditional DLLs, such as small locking range, long locking time, etc. It is quite an interesting research for improving such disadvantages in traditional DLLs.
In this thesis, we design and implement the DLL. Thus, while designing the improved circuit architecture, the fast-locking, wide-range operation, and low jitter are three main considerations. And then for each feature, we have to further improve the original structure to achieve our goals. We present three methods to improve the whole architecture, which is shown as follows:
1. According to the frequency from the input to the DLL, we provide a proper voltage for the loop filter to accelerate the locking time with a programmable charging circuit (PCC). The locking time will be shortened by several times of the period of the clock, which makes a substantial reduction of locking time.
2. A novel frequency multiplier is presented. Less devices are used for the implementation, and thus, the operation range and application of such frequency multiplier will be raised.
3. The tow different delay feedbacks architecture is used. By means of such architecture, we use a tunable delay to generate a new PFD between PFD01 and PFD02 after SW2 turns on. The new PFD has a pseudo dead zone. With two identical PFDs, the input reference signal will be delayed, which will make those two PFDs bounded. With the pseudo dead zone, the output clock of the DLL will have small jitter than with single PFD. The architecture can make the locked output signal have less jitter.
The proposed DLL has been fabricated in 0.18um1P6M CMOS technology. From the simulation results, the proposed DLL-based frequency multiplier can operates in a wide range from 200MHz to 2.2GHz. Meanwhile, at the frequencies in such range, the minimum locking time of the DLL can be as less as six clock cycles. The simulated peak-to-peak jitter of the DLL is 53.6 ps at a frequency of 250MHz. The power consumption of the presented DLL is 31.6mW with a 1.8V supply voltage.
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